This may be related to a bug in one of the accelerated functions, or a problem with the BitBLT engine. The xx chipsets can use MMIO for all communications with the video processor. The and have a 64bit memory bus and thus transfer 8 bytes every clock thus hence the 8 , while the other HiQV chipsets are 32bit and transfer 4 bytes per clock cycle hence the 4. Many laptops use the programmable clock of the x chips at the console. The whole thing is divided by the bytes per pixel, plus an extra byte if you are using a DSTN. The amount of ram required for the framebuffer will vary depending on the size of the screen, and will reduce the amount of video ram available to the modes.

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If this option is removed form xorg. Worst case scenario, i wonder if i could load in a low profile graphics card that’s less trouble and get it to play ball with the internal LCD.

Chips and Technologies – Wikipedia

In its current form, X can not take advantage of this second display channel. The reason for this is that the manufacturer has used the panel timings to get a standard EGA mode to work nad flat panel, and these same timings annd work for an SVGA mode. For the HiQV series of chips, the memory clock can be successfully probed.

If you find you truly can’t achieve the mode you are after with the default clock limitations, look at the options ” DacSpeed ” and ” SetMClk “. It is possible to use the fixed clocks supported by the chip instead by using this option.

The lower half of the screen is not accessible. This can be done by using an external frame technplogies, or incorporating the framebuffer at the top of video ram depending on the particular implementation.


Chips and Technologies (Asiliant) Free Driver Download for Windows XP () – WXPvzip

So the value actually used for the memory clock might be tschnologies less than this maximum value. This is usually due to a problem with the ” LcdCenter ” option.

We recommend that you try and pick a mode that is similar to a standard VESA mode. The driver is capable of chis both a CRT and a flat panel display. The effect of this problem will be that the lower part of the screen will reside in the same memory as the frame accelerator and will therefore be corrupt.

Asiliant Technologies

Please read the section below about dual-head display. That is from 0 to for 8bit depth, 0 to 32, for 15bit depth, etc.

A general problem with the server that can manifested in many way such as drawing errors, wavy screens, etc is related to the programmable clock. An 8bpp snd and a 16bpp one. Note that for the this is required as the base address can’t be correctly probed. This is the first version of the of the ctxx that was capable of supporting Hi-Color and True-Color.

These option individually disable the features of the XAA acceleration code that the Chips and Technologies driver uses. The amount of ram required for the framebuffer will vary depending on the size of the screen, and will reduce the amount of video ram available to the modes. With this option all of the graphics are rendered into a copy of the framebuffer that is keep in the main memory of the computer, and the screen is updated from this copy.

This option might also be used to reduce the speed of the memory clock to preserve power in modes that don’t need the full speed of the memory to work correctly.


At this point no testing has been done and it is entirely possible twchnologies the ” MMIO option will lockup your machine. The Xserver assumes that the framebuffer, if used, will be at the top of video ram. This also gives more memory bandwidth for use in the drawing operations.

This chip is specially manufactured for Toshiba, and so documentation is not widely available. Otherwise it has the the same properties as the On a cold-booted system this might be the appropriate value to use at the text console see the ” TextClockFreq ” optionas 655550 flat panels will need a dot clock different than the default to synchronise.

However some video ram, particularly EDO, might not be fast enough to handle this, resulting in drawing errors on the screen. The authors of this software wish to acknowledge the support supplied by Chips and Technologies during the development of this software. However these numbers take no account of the extra bandwidth needed for DSTN screens.

Many potential programmable clock register setting are unstable. There is no facility in the current Xservers to specify these values, and so the server attempts to read the panel size from the chip. Before using this check that the server reports an incorrect panel size.

The x and WinGine chipsets are capable of colour depths of 16 or 24bpp.